Hello paging world!

Yes, that's right. We've just entered paging mode.

I just made the commit available which solved the issue on the double fault caused by the page fault. The issue came from the halt&catch fire instruction, because it releases after an interrupt.

I had some issues with paging because I didn't map the VGA memory and the Stack.
These two are now solved.

So what is paging precisely?

Paging is using tables in the CPU to translate virtual addresses into actual physically accessible memory.

How do we do that?
Well to explain that we're going to split the memory up in parts. We're also going to split your memory addresses up in parts. Further more we'll expect the Intel CPU to be in 32-bits protected mode, so our linear addresses reach up to 4 GiB.

The memory is divided into pages, each being 4096 bytes (or 4 KiB) in size. So that means we have about 1 million pages. To reference these pages, we're going to need page tables.

Each page table is exactly 1 page in size, with each entry being 4 bytes. That means only 1024 pages can be accessed in a single page table. If you've been paying attention you can see that this only references 0.1% of all the memory space.

That's somewhat of an issue, but because the designers at Intel aren't stupid, they've created what they call a page directory. Now this page directory also holds 1024 entries of a 4 bytes each. These entries point to the page tables. That means we've now got 1024*1024 pages. That's more like it.

Now, if you don't understand the way this works, you should probably read the Intel manual Volume 3A, chapter 6. It also covers PAE and Long mode paging. Further more it holds the flags required for the implementation.

All the cache bits are set to 0, so the default mode gets used.